FIG. 5 is a circuit diagram showing a memory device manufactured in accordance with a first conventional method, in which a ROM composed of single-layer poly silicon NAND cells. Further, FIG. 6 is a plane view showing the actual memory device shown in FIG. 5, and FIG. 7 is a cross-sectional view taken along the line A-B in FIG. 6.
In FIG. 5, a bit line (aluminum wire) 1 is connected in series to two of series-connected transistors Tr1, Tr1; Tr2, Tr2; . . . A pair of the transistors Tr1 are select transistors; and a plurality of the transistors Tr2 are memory transistors. A pair of select lines (poly silicon layer) 2(1) and 2(2) are connected to the gates of a pair of the transistors Tr1, respectively. A plurality of word lines (poly silicon layer) 3(1), 3(2), . . . 3(n) are connected to the gates of the transistors Tr2, respectively.
As shown in FIGS. 6 and 7, the transistors Tr1 are Tr2 are constructed by forming poly silicon layers 2 and 3 (gates) on a semiconductor substrate Sb and between N.sup.+ layers 5 (source and drain layers) formed on the same semiconductor substrate Sb at regular intervals. Further, ion implantation regions 8 are formed by selectively implanting ions to some of the channel regions 8A under the poly silicon layers 2 and 3, respectively. Further, aluminum wires (bit lines) 1 are connected to contacts 7 to read data from the memory transistors Tr2, respectively.
The memory device as described above is manufactured in accordance with the first conventional method as follows: first, the gates of transistors Tr1 and Tr2 are formed on the surface portion of a semiconductor substrate Sb by forming poly silicon layers 2 and 3. Further, the sources and the drains thereof are formed by forming an N.sup.+ layer 5. Thereafter, data are written by selectively implanting ions into the channel regions 8A with the use of a mask (not shown) formed on the basis of data to be stored therein. In other words, the transistors operate in different way according to the presence or absence of ion implantation into the channel regions 8A, respectively. Therefore, data can be written in the respective transistors Tr1 and Tr2 by use of the programmed mask for ion implantation, and then the written data can be read.
FIG. 8 is a cross-sectional view showing the memory device manufactured in accordance with a second conventional method, in which a double-layer poly silicon NAND memory device is shown in particular. In the case of this structure, the ion implantation regions 8 are formed by selectively implanting ions into some of the channel regions 8A with the use of an ion implantation mask programmed on the basis of data to be first stored, so that the channel regions 8A can be selectively formed into depletion mode to store data. Thereafter, a first poly silicon layer 9 is formed on the semiconductor substrate Sb, and further a second poly silicon layer 10 is formed on the channel regions 8A to form gate electrodes. Then, the N.sup.+ layer 5 is formed.
In the double-layer poly silicon NAND masked ROM manufactured as shown in FIG. 8, there exists no N.sup.+ layer as the sources and the drains of the transistors from the structural standpoint, as well understood by the comparison between two first and second conventional methods as shown in FIGS. 7 and 8. Accordingly, the transistors can be arranged at a high density. Further, data can be read to the outside through the first poly silicon layers 9 when the second poly silicon layers 10 are activated as the gate electrodes.
In the above-mentioned two memory devices manufactured in accordance with two different conventional methods as shown in FIGS. 7 and 8, there exist different problems as follows: In the case of the single-layer poly silicon NAND masked ROM manufactured in accordance with the first conventional method as shown in FIGS. 5 to 7, it is difficult to arrange the transistors at a high density. In contrast with this, in the case of the double-layer poly silicon NAND ROM manufactured in accordance with the second conventional method as shown in FIG. 8, it is possible to arrange the transistors at a high density. On the other hand, however, since the ion implantation regions 8 must be determined to be broader than the channel regions 8A under due consideration of mask offset, there raises another problem in that ions are implanted into the adjacent channel regions, thus causing a deterioration of production yield. Further, it may be possible to prevent ions from being implanted into the adjacent regions by forming long channels. In this countermeasures, however, the transistors cannot be arranged at high density.
Further, in the case of the single-layer poly silicon NAND masked ROM as shown in FIGS. 5 to 7, in order to shorten the turn-around time, in general there has been adopted such a method of implanting ions into the channel regions from above after the gates 2 and 3 have been formed. In contrast with this, in the case of the double-layer poly silicon NAND masked ROM, ions are not easily implanted through the overlapped portions of the first poly silicon layer 9 and the second poly silicon layer 10 under the ordinary ion implantation conditions. Therefore, these overlapped portions are left in enhancement mode ever after the ion implantation, with the result that the device cannot be operated as the NAND masked ROM. To overcome this problem, conventionally, ions are implanted before forming the gates of the first poly silicon layer 9, at the sacrifice of the reduction of the turn-around time.